SMS44S View Datasheet(PDF) - Summit Microelectronics
Part Name
Description
View to exact match
SMS44S Datasheet PDF : 16 Pages
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SMS44
Master
SDA
Slave
S
T
A
R Device Type Bus
T Address Address
Typical Write Operation
(Standard memory device type)
1
0
1
0
B
A
2
B
A
1
A
8
R
/
W
A AA A AA AA
7 65 4 32 10
DDDDDDDD
76543210
A
A
A
C
C
C
K
K
K
S
T
Master
A
R
Typical Reading Operation
(Alternate memory device type)
A
C
A
C
T
K
K
SDA
BB R
10
11
A
2
A
1
A/
8W
A A A A AA AA
7 6 5 4 32 10
DDDDDDDD
76543210
Slave
A
C
K
S
T
O
P
Up to 15
additional bytes
can be written
before issuing
the stop.
S
T
O
P
The host may continue
clocking out data so long as
it provides an ACK response
after each byte.
S
T
Master
A
R
Writing Configuration Registers
S
T
O
T
P
SDA
BB R
1 00 1 A A X /
21 W
CCCCCCCC
76543210
DDDDDDDD
76543210
Slave
A
A
A
C
C
C
K
K
K
S
S
T
Master
A
R
Reading the Configuration Register
T
A
C
K
T
A
R
T
SDA
BB R
1 00 1 A A X /
21 W
CCCCCCCC
76543210
BB R
1
00
1
A
2
A
1
X/
W
A
C
K
S
T
O
P
DDDDDDDD
76543210
Slave
A
C
K
A
C
K
2047 Fig10 2.1
Figure 10. Read and Write Operations
The high order bits of the address byte remain constant.
Should the master transmit more than 16 bytes, prior to
generating the STOP condition, the address counter will
“roll over” and the previously written data will be overwrit-
ten. As with the byte-write operation, all inputs are
disabled during the internal write cycle. Refer to Figure 10
for the address, ACKnowledge, and data transfer se-
quence.
SUMMIT MICROELECTRONICS, Inc.
2047 2.3 10/23/00
13
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