IDT71V424L(2013) View Datasheet(PDF) - Integrated Device Technology
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Description
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IDT71V424L Datasheet PDF : 9 Pages
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IDT71V424S, IDT71V424L, 3.3V CMOS Static RAM
4 Meg (512K x 8-bit)
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VCC = 3.3V ± 10%, Commercial and Industrial Temperature Ranges)
Symbol
READ CYCLE
tRC
Read Cycle Time
tAA
Address Access Time
tACS
Chip Select Access Time
Parameter
71V424S/L10
71V424S/L12
71V424S/L15
Min. Max. Min. Max. Min. Max. Unit
10
____
12
____
15
____
ns
____
10
____
12
____
15
ns
____
10
____
12
____
15
ns
tCLZ(1)
Chip Select to Output in Low-Z
4
____
4
____
4
____
ns
tCHZ(1)
tOE
tOLZ(1)
Chip Deselect to Output in High-Z
Output Enable to Output Valid
Output Enable to Output in Low-Z
____
5
____
6
____
7
ns
____
5
____
6
____
7
ns
0
____
0
____
0
____
ns
tOHZ(1)
tOH
Output Disable to Output in High-Z
Output Hold from Address Change
____
5
____
6
____
7
ns
4
____
4
____
4
____
ns
tPU(1)
Chip Select to Power Up Time
0
____
0
____
0
____
ns
tPD(1)
Chip Deselect to Power Down Time
WRITE CYCLE
tWC
Write Cycle Time
tAW
Address Valid to End of Write
tCW
Chip Select to End of Write
tAS
Address Set-up Time
tWP
Write Pulse Width
tWR
Write Recovery Time
tDW
Data Valid to End of Write
tDH
Data Hold Time
____
10
____
12
____
15
ns
10
____
12
____
15
____
ns
8
____
8
____
10
____
ns
8
____
8
____
10
____
ns
0
____
0
____
0
____
ns
8
____
8
____
10
____
ns
0
____
0
____
0
____
ns
6
____
6
____
7
____
ns
0
____
0
____
0
____
ns
tOW(1)
Output Active from End of Write
3
____
3
____
3
____
ns
tWHZ(1)
Write Enable to Output in High-Z
____
6
____
7
____
7
ns
NOTE:
1. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested.
3622 tbl 10
6.452
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