CS61881
TDI
TCK
TRSTB
TMS
Digital output pins Digital input pins
parallel latched
output
Boundary Scan Data Register
Device ID Data Register
Bypass Data Register
Instruction (shift) Register
parallel latched
output
TAP
Controller
JTAG Block
MUX
TDO
Figure 5. Test Access Port Architecture
1
Test-Logic-Reset
0
1
0
Run-Test/Idle
Select-DR-Scan 1
0
1
Capture-DR
0
Shift-DR
0
1
1
Exit1-DR
0
Pause-DR
0
1
0
Exit2-DR
1
Update-DR
1
0
Select-IR-Scan
0
1
Capture-IR
0
Shift-IR
1
Exit1-IR
0
Pause-IR
1
0
Exit2-IR
1
Update-IR
1
0
1
0
1
0
Figure 6. TAP Controller State Diagram
DS451PP3
11